Search - DDS Verilog

[VHDL-FPGA-Verilog] DDS

Description: 用verilog语言实现，DDS信号发生与嵌入式逻辑分析仪的调用，程序功能完整 -Using verilog language, DDS signal generator with embedded logic analyzer called, the program features a complete
Platform: | Size: 9216 | Author: | Hits:

[VHDL-FPGA-Verilog] DDS

Description: FPGA产生DDS，未使用IP核，内含VERILOG程序-FPGA generates DDS, unused IP core, containing VERILOG program
Platform: | Size: 585728 | Author: bodao | Hits:

[Other] DDS_2013_7_7_updata_past_v0.1

Description: DDS verilog，自己写的，验证通过！-DDS verilog made by myself,and test past!
Platform: | Size: 4504576 | Author: paul | Hits:

[Documents] cordic

Description: 基于cordic算法的DDS的Verilog代码。经过仿真验证，绝对可靠。-Based on cordic algorithm DDS Verilog code. Through the simulation, is absolutely reliable.
Platform: | Size: 1985536 | Author: longgege | Hits:

[VHDL-FPGA-Verilog] dds

Description: 在altera的FPGA上实现直接数字频率合成，即用verilog实现DDS，输出正弦波形，在modelsim软件中仿真通过，已包含所有代码和工程以及二进制流文件。-The realization of direct digital frequency synthesis in the Altera FPGA, which is implemented by Verilog DDS, the output sine wave, through the simulation in Modelsim software, already contains all the code and engineering as well as binary stream file.
Platform: | Size: 694272 | Author: 汪少锋 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 采用硬件描述语言verilog进行DDS变换的实现的代码-Using hardware description languages Verilog implementation of DDS converter code
Platform: | Size: 1024 | Author: 何晨光 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 用Verilog HDL 编写的一个最基本的DDS程序，发生正弦波-Verilog HDL prepared with a basic DDS program, the occurrence of a sine wave
Platform: | Size: 890880 | Author: 董航 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: Verilog HDL实现FPGA的DDS功能，含有实验原理与代码程序-FPGA Verilog HDL realize the DDS function, principles and codes containing experimental procedures
Platform: | Size: 893952 | Author: 秦天沐 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于fpga的正余弦波形发生器，Verilog代码，测试通过。-Cosine waveform generator fpga based, Verilog code, the test passes.
Platform: | Size: 4471808 | Author: 黄迟 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于fpga的DDS详细设计方案 verilog语言正弦计算器则对该相位值计算数字化正弦波幅度（芯片一般通过查表得到）。DDS芯片输出的一般是数字化的正弦波，因此还需经过高速D/A转换器和低通滤波器才能得到一个可用的模拟频率信号。-Direct Digital Synthesizer base on fpga use verilog Sine calculator to calculate the value of the digital phase sine wave amplitude (chips generally obtained through look-up table). Generally digitized sine wave output of DDS chip, and therefore need to go through the high-speed D/A converter and a low pass filter to get an analog frequency signal available.
Platform: | Size: 5949440 | Author: 网窝囊 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: verilog编写，使用fpga中dds手法，可以输出任意波形的发生信号。-verilog write, use the dds fpga way, you can output an arbitrary waveform signal occurs.
Platform: | Size: 506880 | Author: 李俊 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 在quartus软件上，采用verilog实现DDS功能。- using verilog realize DDS function On quartus software.
Platform: | Size: 2166784 | Author: 刘云 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 这是本人在学校做的一个DDS信号发生器，频率相位可调。输入时钟50Mhz-DDS phase frequency adjustable Verilog
Platform: | Size: 2437120 | Author: wen show | Hits:

[VHDL-FPGA-Verilog] DDS

Description: Verilog实现DDS线性调频，Verilog实现DDS线性调频-Verilog implementation of DDS linear FM，Verilog implementation of DDS linear FM
Platform: | Size: 1024 | Author: youyou | Hits:

[VHDL-FPGA-Verilog] DDS

Description: FPGA基于FPGA的DDS设计verilog程序-FPGA DDS project verilog procedure
Platform: | Size: 10240 | Author: 吴汉 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: FPGA实现三通道DDS信号源Verliog程序-FPGA to achieve three-channel DDS signal source Verilog program
Platform: | Size: 9389056 | Author: 果粒橙 | Hits:

[VHDL-FPGA-Verilog] DDS(ok)

Description: 制作ROM正弦表并填充FPGA内部ROM，通过调用内部数据实现正弦波输出，开发环境quartusii , 语言verilog , 调试通过，附有modelsim调试结果。-Make ROM sine table and fill the ROM internal FPGA, by calling the internal data to achieve the sine wave output, development environment QuartusII, Language Verilog, debugging through, with Modelsim debugging results.
Platform: | Size: 10149888 | Author: PrudentMe | Hits:

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[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[Other] DDS_2013_7_7_updata_past_v0.1

[Documents] cordic

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS(ok)

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] dds_synthesizer

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